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| TDA7500A DIGITAL AM/FM SIGNAL PROCESSOR s s s s s s s s s s s s s FULL SOFTWARE FLEXIBILITY WITH TWO 24X24 BIT DSP CORES SOFTWARE AM/FM, AUDIO AND SOUNDPROCESSING HARDWARE RDS FILTER, DEMODULATOR & DECODER INTEGRATED CODEC (4ADCs, 6DACs) IIC AND SPI CONTROL INTERFACES SPI DEDICATED TO DISPLAY MICRO 6 CHANNEL SERIAL AUDIO INTERFACE (SAI) SPDIF RECEIVER WITH SAMPLE RATE CONVERTER EXTERNAL MEMORY INTERFACE (EMI) DOUBLE DEBUG INTERFACE ON-CHIP PLL 5V-TOLERANT 3V I/O INTERFACE 12x2 MULTIFUNCTION GENERAL PURPOSE I/O PORTS TQFP100 (with slug down) ORDERING NUMBER: TDA7500A DESCRIPTION The TDA7500A is an integrated circuit implementing a fully digital, integrated and advanced solution to perform the signal processing in front of the power amplifier and behind the AM/FM tuner or any other audio source. The chip integrates two 45 MIPs DSP cores: one for stereo decoding, noise blanking, weak signal processing and multipath detection and one for sound processing, Dolby B, echo and noise cancelling for the telephone. BLOCK DIAGRAM analog in analog audio out ADC-ref Decimation Filter Decimation Filter PLL Clock Generator SC Filter SC Filter SC Filter SC Filter SC Filter SC Filter DAC-ref Noise Shaper Noise Shaper Noise Shaper ADCVDD ADCGND AVDD AGND CLK in Crystal Oscillator Oversampl. Oversampl. Oversampl. Filter Filter Filter Grp & blk sync., error correction IIC / SPI 1 SPI 2 SAI Transmitter External Memory Interface SRAM 4Mx8 DRAM 128kx4 RDS Filter Demod. SPI Error corr. RDS blocks or RDS clk, dat, qual RDS RDS bit/blk Int. 4 RDS SPI 4 10 word SPI 1 receive stack 2ch Sample Rate Converter 4 3 2 8+3 17 P control 6 Ch. Audio Bus 2 receive bit&word clk digital audio in SPDIF audio in Display P 6 Channel Audio Bus SAI 6ch. Receiver SPDIF 2ch. Interface DSP1 Orpheus Core including 12 GPIOs DSP0 Orpheus Core X Ram 1024 Y Ram 1024 P Ram 2048 P Rom 256 Xchg Interf. including 12 GPIOs Int Reset 4 4 2 Test 4 VDD GND Dolby B FM processing, AM processing, Traffic memorization 4 Debug Interface X Ram 1024 Y Ram 1024 P Ram 5632 P Rom 512 Audio processing, Sound processing, Noise & Echo Canc. Debug Interface December 2001 1/40 TDA7500A DESCRIPTION (continued) An I2C/SPI interface is implemented for control and communication with the main micro. A separate SPI is available to interface the display micro.The DSP cores are integrated with their associated data and program memories. The peripherals and interfaces I 2C, SPI, Serial Audio Interface (SAI), PLL Oscillator, External Memory Interface, (EMI), General Purpose I/O register (Port A) and the D/A registers are connected to and controlled by DSP0, whereas the A/D registers, the SPDIF and the General Purpose I/O register (Port B) are connected to and controlled by DSP1. An hardware RDS filter , demodulator and decoder block is also embedded. No support is needed from the DSPs but at initialisation so that RDS can work in background and in parallel with other DSP processing. Separated Debug and Test Interfaces are connected to both DSP cores. The TDA7500A is supposed to be used in kit with the TDA7501 or any other device of the same family. Thanks to the serial audio interface also digital sources can be processed and a direct output to a digital bus is also available. The flexibility allowed by the wide memory space and by the two powerfull DSP cores make the TDA7500A usable for different applications. In example, inside the main radio as an audio co-processor or to perform the signal processing and equalisation associated to a digital power amplifier. ABSOLUTE MAXIMUM RATINGS Symbol VDD VCC Vaio Vdio Vdi5 Tj Tstg Power supplies Parameter Digital Analog Value -0.5 to +4.6 -0.5 to +4.6 -0.5 to (VCC+0.5) -0.5 to (VDD+0.5) -0.5 to 6.5 -40 to 125 -55 to 150 Unit V V V V V C C Analog Input and Output Voltage Digital Input and Output Voltage Digital Input Voltage (5V tolerant) Operating Junction Temperature Range Storage Temperature Warning: Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. THERMAL DATA Symbol Rth j-amb Parameter Thermal resistance junction to ambient (1) Thermal resistance junction to ambient (2) Rth j-case Thermal junction to case (3) Value 45 20 5 Unit C/W C/W C/W Note: 1. In still air 2. On 4 layers board with soldered slug 3. Measured on top side of the package 2/40 TDA7500A PIN DESCRIPTION N 1 2 3 GND1 VDD1 TESTEN I Name Type Description Ground pin dedicated to the digital circuitry. Supply pin dedicated to the digital circuitry. Test Enable (Input). When low, puts the chip into test mode and muxes the XTI clock to all flip-flops. When TEST_SE is also active, the scan chain shifting is enabled. To be connected to Vdd in operating mode. SCAN Enable (Input). When high with TESTEN also active, controls the shifting of the internal scan chains. When active with TESTEN not active, sets all tri-state outputs into hi-impedance mode. To be connected to GND in operating mode. System Reset (Input). A low level applied to NRESET input initializes the IC. I2C Serial Clock Line (Input/Output)/SPI Bit Clock (Input)/ General Purpose I/O (Input/Output). Clock line for I2C bus. If SPI interface is enabled, behaves as SPI bit clock. Optionally it can be used as general purpose I/O controlled by DSP0. I2C Serial Data Line (Input/Output)/SPI Master Input Slave Output Serial Data (Input/Output)/General Purpose I/O (Input/ Output). Data line for I2C bus. If SPI is enabled, behaves as Serial Data Input when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Master Output Slave Input Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Serial Data Output when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Slave Select (Input)/General Purpose I/O (Input/Output). If SPI is enabled, behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Bit Clock (Input)/General Purpose I/O (Input/Output). SPI bit clock. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Master Input Slave Output Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Behaves as Serial Data Input when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. Optionally it can be used as general purpose I/ O controlled by DSP0. SPI Master Output Slave Input Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Serial Data Output when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. SPI Slave Select (Input)/General Purpose I/O (Input/Output). Behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0. 4 TESTSE I 5 6 NRESET SCKM/DSP0_GPIO0 I I/O 7 MISOM/DSP0_GPIO1 I/O 8 MOSIM/DSP0_GPIO2 I/O 9 SSM/DSP0_GPIO3 I 10 SCKD/DSP0_GPIO4 I 11 MISOD/DSP0_GPIO5 I/O 12 MISOD/DSP0_GPIO6 I/O 13 SSD/DSP0_GPIO7 I 3/40 TDA7500A PIN DESCRIPTION (continued) N 14 15 16 17 18 19 CLKIN AVDD XTI XTO AGND RDSINT/DSP1_GPIO4 O I O Name Type I Description Clock Input pin (Input). Clock from external digital audio source to synchronize the internal PLL. Supply pin dedicated to the PLL. Crystal Oscillator Input (Input). External Clock Input or crystal Oscillator input. Crystal Oscillator Output (Output). Crystal Oscillator output drive. Ground pin dedicated to the PLL. RDS bit/block interrupt (Output)/General Purpose I/O (Input/ Output). Provides an interrupt to the main micro. Optionally it can be used as general purpose I/O controlled by DSP1. SPI Bit Clock (Input)/ARI indicator (Output)/General Purpose I/O (Input/Output). If SPI interface is enabled, behaves as SPI bit clock. Optionally it provides the ARI indication bit. Optionally it can be used as general purpose I/O controlled by DSP1. SPI Slave Output Serial Data (Output)/RDS Bit Quality (Output)/ General Purpose I/O (Input/Output). If SPI is enabled, behaves as Serial Data Output. Optionally it provides the RDS serial data quality information. Optionally it can be used as general purpose I/O controlled by DSP1. SPI Slave Input Serial Data (Input)/RDS Bit Data (Output)/ General Purpose I/O (Input/Output). If SPI is enabled, behaves as Serial Data Input. Optionally it provides the RDS serial data stream. Optionally it can be used as general purpose I/O controlled by DSP1. SPI Chip Select (Input)/RDS Bit Clock (Output)/General Purpose I/O (Input/Output). If SPI is enabled, behaves as Chip Select line for SPI bus. Optionally it provides the 1187.5Hz RDS Bit Clock. Optionally it can be used as general purpose I/O controlled by DSP1. External interrupt line (Input). When this line is asserted low, the DSP may be interrupted. Acts as IRQA line of DSP0 core. Ground pin dedicated to the digital circuitry. Supply pin dedicated to the digital circuitry. I I I/O I/O SPDIF Input 1 (Input). Stereo SPDIF input to connect a digital audio source like a CD. SPDIF Input 2 (Input). Stereo SPDIF input to connect a digital audio source like a MD. DSP SRAM Data Lines<7> (Input/Output). When in SRAM Mode this pin act as the EMI data line 7. DSP SRAM Data Lines<6> (Input/Output). When in SRAM Mode this pin act as the EMI data line 6. 20 RDSARI_SCK/DSP1_GPIO3 O 21 RDSQAL_SO/DSP1_GPIO2 O 22 RDSDAT_SI/DSP1_GPIO1 I 23 RDSCLK_SS/DSP1_GPIO0 I 24 25 26 27 28 29 30 INT CGND1 CVDD1 SCRCCD SCRMD DSRA<7> DSRA<6> I 4/40 TDA7500A PIN DESCRIPTION (continued) N 31 32 33 DSRA<5> DSRA<4> DSRA<3> Name Type I/O I/O I/O Description DSP SRAM Data Lines<5> (Input/Output). When in SRAM Mode this pin act as the EMI data line 5. DSP SRAM Data Lines<4> (Input/Output). When in SRAM Mode this pin act as the EMI data line 4. DSP SRAM Data Lines<3> (Input/Output)/DSP DRAM Data Line<3>(Input/Output). This pin act as the EMI data line 3 in both SRAM Mode and DRAM Mode. DSP SRAM Data Lines<2> (Input/Output)/DSP DRAM Data Line<2>(Input/Output). This pin act as the EMI data line 2 in both SRAM Mode and DRAM Mode. DSP SRAM Data Lines<1> (Input/Output)/DSP DRAM Data Line<1>(Input/Output). This pin act as the EMI data line 1 in both SRAM Mode and DRAM Mode. DSP SRAM Data Lines<0> (Input/Output)/DSP DRAM Data Line<0>(Input/Output). This pin act as the EMI data line 0 in both SRAM Mode and DRAM Mode. DSP SRAM Address Line<0> (Output)/DSP DRAM Address Line<0> (Output). This pin acts as the EMI address line 0 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<1> (Output)/DSP DRAM Address Line<1> (Output). This pin acts as the EMI address line 1 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<2> (Output)/DSP DRAM Address Line<2> (Output). This pin acts as the EMI address line 2 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<3> (Output)/DSP DRAM Address Line<3> (Output). This pin acts as the EMI address line 3 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<4> (Output)/DSP DRAM Address Line<4> (Output). This pin acts as the EMI address line 4 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<5> (Output)/DSP DRAM Address Line<5> (Output). This pin acts as the EMI address line 5 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<6> (Output)/DSP DRAM Address Line<6> (Output). This pin acts as the EMI address line 6 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<7> (Output)/DSP DRAM Address Line<7> (Output). This pin acts as the EMI address line 7 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<8> (Output)/DSP DRAM Address Line<8> (Output). This pin acts as the EMI address line 8 in both SRAM Mode and DRAM Mode 34 DSRA<2> I/O 35 DSRA<1> I/O 36 DSRA<0> I/O 37 SRA<0> O 38 SRA<1> O 39 SRA<2> O 40 SRA<3> O 41 SRA<4> O 42 SRA<5> O 43 SRA<6> O 44 SRA<7> O 45 SRA<8> O 5/40 TDA7500A PIN DESCRIPTION (continued) N 46 SRA<9> Name Type O Description DSP SRAM Address Line<9> (Output)/DSP DRAM Address Line<9> (Output). This pin acts as the EMI address line 9 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<10> (Output)/DSP DRAM Address Line<10> (Output). This pin acts as the EMI address line 10 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<11> (Output)/DSP DRAM Address Line<11> (Output). This pin acts as the EMI address line 11 in both SRAM Mode and DRAM Mode DSP SRAM Address Line<12> (Output)/DSP DRAM Address Line<12> (Output). This pin acts as the EMI address line 12 in both SRAM Mode and DRAM Mode Ground pin dedicated to the digital circuitry. Supply pin dedicated to the digital circuitry. O DSP SRAM Address Line<13> (Output)/DSP DRAM Address Line<13> (Output). This pin act as the EMI address line 13 in both SRAM Mode and DRAM Mode. DSP SRAM Address Line<14> (Output)/DSP DRAM Address Line<14> (Output). This pin act as the EMI address line 14 in both SRAM Mode and DRAM Mode. DSP SRAM Address Line<15> (Output)/DSP DRAM Address Line<15> (Output). This pin act as the EMI address line 15 in both SRAM Mode and DRAM Mode. DSP SRAM Address Line<16> (Output)/DSP DRAM Address Line<16> (Output)/General Purpose I/O (Input/Output). This pin acts as the EMI address line 16 in both SRAM Mode and DRAM Mode. Optionally it can be used as general purpose I/O controlled by DSP0. After reset the state of this pin is read by the boot SW to select the boot mode (Refer to HW/SW maual). DSP SRAM Write Enable (Output)/DRAM Write Enable (Output). This pin serves as the write enable for the EMI in both DRAM and SRAM Mode (active low). To be connected to R/W of the RAM. DSP SRAM Read Enable(Output)/DRAM Read Enable (Output). This pin serves as the read enable for the EMI in both DRAM and SRAM Mode (active low). To be connected to R/W of the RAM. DSP DRAM Column Address Strobe (Output). When in DRAM Mode this pin acts as the column address strobe. SAI Outputs (Output)/EMI SRAM Address Line<17> (Output)/ General Purpose I/O (Input/Output). One stereo channel SAI data output in SAI mode. EMI address line 17 in SRAM Mode. Optionally it can be used as a general purpose I/O. 47 SRA<10> O 48 SRA<11> O 49 SRA<12> O 50 51 52 CGND2 CVDD2 SRA<13> 53 SRA<14> O 54 SRA<15> O 55 SRA<16>/DSP0_GPIO8 O 56 DWR O 57 DRD O 58 59 CASALE SDO<2>/SRA<17>/DSP1_GPIO<8> O O 6/40 TDA7500A PIN DESCRIPTION (continued) N 60 Name SDO<2>/SRA<18>/DSP1_GPIO<7> Type O Description SAI Outputs (Output)/EMI SRAM Address Line<18> (Output)/ General Purpose I/O (Input/Output). One stereo channel SAI data output in SAI mode. EMI address line 18 in SRAM Mode. Optionally it can be used as a general purpose I/O. SAI Output (Output)/EMI SRAM Address Line<19> (Output). One stereo channel SAI data output in SAI mode. EMI address line 19 in SRAM Mode. SAI Input (Input)/EMI SRAM Address Line<20> (Output)/ General Purpose I/O (Input/Output). One stereo channel SAI data input in SAI mode. EMI address line 20 in SRAM Mode. Optionally it can be used as a general purpose I/O. SAI Input (Input)/EMI SRAM Address Line<21> (Output)/DRAM Row Address Strobe (Output)/General Purpose I/O (Input/ Output). One stereo channel SAI data input in SAI mode. EMI address line 21 in SRAM Mode. When in DRAM Mode this pin acts as the row address strobe. Optionally it can be used as a general purpose I/O. SAI Input (Input)/SPDIF Input 3 (Input). One stereo channel SAI data input in SAI mode. Stereo SPDIF input intended to connect a digital audio source like a CD changer in SPDIF mode. SAI transmitter Bit Clock (Input/Output). SAI transmitter bit clock. Master or slave. SAI transmitter Left-Right Clock (Input/Output). SAI transmitter Left-Right clock. Can be master or slave mode. SAI receiver Bit Clock (Input). SAI receiver bit clock. Slave only. SAI receiver Left-Right Clock (Input/Output). SAI receiver LeftRight clock. Slave only. Debug Port Serial Output (Input/Output)/ General Purpose I/O (Input/Output). The serial data output for the Debug Port. Optionally it can be used as a general purpose I/O. Debug Port Serial Input/Chip Status 0 (Input/Output)/ General Purpose I/O (Input/Output). The serial data input for the Debug Port is provided when an input. When an output, together with OS1 provides information about the chip status. Optionally it can be used as a general purpose I/O. Debug Port Bit Clock/Chip Status 1 (Input/Output)/General Purpose I/O (Input/Output). The serial clock for the Debug Port is provided when an input. When an output, together with OS0 provides information about the chip status. Optionally it can be used as a general purpose I/O. Debug Port Request Input (Input). Means of entering the Debug mode of operation. Debug Port Serial Output (Input/Output)/ General Purpose I/O (Input/Output). The serial data output for the Debug Port. Optionally it can be used as a general purpose I/O. 61 SDO<0>/SRA<19> O 62 SDI<2>/SRA<20>/DSP1_GPIO<6> I 63 SDI<1>/SRA<21>/RAS/DSP1_GPIO<5> I 64 SDI<0>/SRCCDC I 65 66 67 68 69 SCKT LRCKT SCKR LRCKR DBOUT1/DSP1_GPIO10 I/O I/O I I I/O 70 DBIN1/OS10/DSP1_GPIO11 I/O 71 DBCK1/OS11/DSP1_GPIO9 I/O 72 73 DBRQN1 DBOUT0/DSP0_GPIO10 I I/O 7/40 TDA7500A PIN DESCRIPTION (continued) N 74 Name DBIN0/OS00/DSP0_GPIO11 Type I/O Description Debug Port Serial Input/Chip Status 0 (Input/Output)/ General Purpose I/O (Input/Output). The serial data input for the Debug Port is provided when an input. When an output, together with OS1 provides information about the chip status. Optionally it can be used as a general purpose I/O. Debug Port Bit Clock/Chip Status 1 (Input/Output)/General Purpose I/O (Input/Output). The serial clock for the Debug Port is provided when an input. When an output, together with OS0 provides information about the chip status. Optionally it can be used as a general purpose I/O. Debug Port Request Input (Input). Means of entering the Debug mode of operation. Supply pin dedicated to the digital circuitry. Ground pin dedicated to the digital circuitry. I I I I I I I I I Analog Inputs (Input). Single ended analog signal inputs to the ADC. Analog Inputs (Input). Single ended analog signal inputs to the ADC. Analog Inputs (Input). Single ended analog signal inputs to the ADC. Analog Inputs (Input). Single ended analog signal inputs to the ADC. To be connected to ADCGND Voltage Reference (Input). Analog voltage reference input. Signal is supplied by A354. (typical 3.3V). Voltage Reference (Input). External decoupling of the analog references used for the sigma delta modulator. Voltage Reference (Input). External decoupling of the analog references used for the sigma delta modulator. Voltage Reference (Input). External decoupling of the analog references used for the sigma delta modulator. Analog Supply pin dedicated to the A/D converter. Analog Ground pin dedicated to the A/D converter. O O O O O O Analog Outputs (Output). Analog signal outputs of the DAC Analog Outputs (Output). Analog signal outputs of the DAC Analog Outputs (Output). Analog signal outputs of the DAC Analog Outputs (Output). Analog signal outputs of the DAC Analog Outputs (Output). Analog signal outputs of the DAC Analog Outputs (Output). Analog signal outputs of the DAC 75 DBCK0/OS01/DSP0_GPIO9 I/O 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 DBRQN0 VDD2 GND2 ADC<0> ADC<1> ADC<2> ADC<3> S2DREF ADCVDDREF ADCREF<2> ADCREF<1> ADCREF<0> ADCVDD ADCGND DAC<0> DAC<1> DAC<2> DAC<3> DAC<4> DAC<5> I 8/40 TDA7500A PIN DESCRIPTION (continued) N 96 97 98 99 100 DACREF<2> DACREF<1> DACREF<0> DACGND DACVDD Name Type I I I Description Voltage Reference (Input). External decoupling of the analog references of the CODEC and voltage biasing. Voltage Reference (Input). It can be connected to pin 100. Voltage Reference (Input). External decoupling of the analog references of the CODEC and voltage biasing. Analog Ground pin dedicated to the D/A converter. Analog Supply pin dedicated to the D/A converter. I/O DEFINITION AND STATUS O: logic low output X: undefined input/output Z: high impedance 1: logic input output Pin # 1 2 3 4 5 6 GND1 VDD1 TESTEN TESTSE NRESET MSPI: SCKM input MSPI: SCKM output I2C: SCL bi-direct DSP0: GPIO0 input DSP0: GPIO0 output MSPI: MISOM input MSPI: MISOM output I2C: SDA bi-direct DSP0: GPIO1 input DSP0: GPIO1 output MSPI: MOSIM input MSPI: MOSIM output DSP0: GPIO2 input DSP0: GPIO2 output MSPI: SSM input DSP0: GPIO3 input DSP0: GPIO3 output DSPI: SCKD input DSPI: SCKD output DSP0: GPIO4 input DSP0: GPIO4 output X X X X X X X (1) X X 0 or 1 X X X X X X X X X X X X X X X X (1) X X X X X X Function Reset State After Boot SPI I2C I/O EMI supply supply input input input 5VT input 5VT (1) undefined output 4mA PP input input 5VT/output 4mA OD input 5VT output 4mA OD input 5VT output 4mA OD input 5VT/output 4mA OD input 5VT output 4mA PP input 5VT output 4mA OD input 5VT output 4mA OD input 5VT input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP To be connected to VDD To be connected to GND Ext. Pulldown Comments 7 8 9 10 9/40 TDA7500A I/O DEFINITION AND STATUS (continued) Pin # 11 Function DSPI: MISOD input DSPI: MISOD output DSP0: GPIO5 input DSP0: GPIO5 output DSPI: MOSID input DSPI: MOSID output DSP0: GPIO6 input DSP0: GPIO6 output DSPI: SSD input DSP0 : GPIO7 input DSP0 : GPIO7 output PLL: CLKIN input PLL: AVDD PLL: XTI input PLL: XTO output PLL: AGND RDS: RDSINT output DSP1: GPIO4 input DSP1: GPIO4 output RDS: RDSARI output RDS SPI: SCK input DSP1: GPIO3 input DSP1: GPIO3 output RDS: RDSQAL output RDS SPI: SO input DSP1: GPIO2 input DSP1: GPIO2 output RDS: RDSDAT output RDS SPI: SI input DSP1: GPIO1 input DSP1: GPIO1 output RDS: RDSCLK output RDS SPI: SS input DSP1: GPIO0 input DSP1: GPIO0 output INT input CGND1 CVDD1 SCRCCD input SCRCMD input EMI SRAM: Data<7> bi-direct X X 1 X X 1 X X 1 X X Z X X X X X X X X X X X X X Reset State After Boot SPI X X X X X X X X X I2C X I/O EMI X input 5VT output 4mA OD input 5VT output 4mA OD input 5VT output 4mA OD input 5VT output 4mA OD input 5VT input 5VT output 4mA PP input supply analog input analog output supply output 4mA PP onput 5VT output 4mA PP output 4mA PP input 5VT input 5VT output 4mA PP output 4mA OD output 4mA OD input 5VT output 4mA OD output 4mA PP input 5VT input 5VT output 4mA PP output 4mA PP input 5VT input 5VT output 4mA PP input 5VT supply supply input 5VT input 5VT input/output 2mA PP Ext. Pullup max. 20 MHz Comments 12 13 14 15 16 17 18 19 X X X 20 X X X X 21 X X X X 22 X X X X 23 X X X X X X X X 24 25 26 27 28 29 10/40 TDA7500A I/O DEFINITION AND STATUS (continued) Pin # 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function EMI SRAM: Data<6> bi-direct EMI SRAM: Data<5> bi-direct EMI SRAM: Data<4> bi-direct EMI SRAM: Data<3> bi-direct EMI SRAM: Data<3> bi-direct EMI SRAM: Data<2> bi-direct EMI SRAM: Data<2> bi-direct EMI SRAM: Data<1> bi-direct EMI SRAM: Data<1> bi-direct EMI SRAM: Data<0> bi-direct EMI SRAM: Data<0> bi-direct EMI SRAM: Add<0> output EMI SRAM: Add<0> output EMI SRAM: Add<1> output EMI SRAM: Add<1> output EMI SRAM: Add<2> output EMI SRAM: Add<2> output EMI SRAM: Add<3> output EMI SRAM: Add<3> output EMI SRAM: Add<4> output EMI SRAM: Add<4> output EMI SRAM: Add<5> output EMI SRAM: Add<5> output EMI SRAM: Add<6> output EMI SRAM: Add<6> output EMI SRAM: Add<7> output EMI SRAM: Add<7> output EMI SRAM: Add<8> output EMI SRAM: Add<8> output EMI SRAM: Add<9> output EMI SRAM: Add<9> output EMI SRAM: Add<10> output EMI SRAM: Add<10> output EMI SRAM: Add<11> output EMI SRAM: Add<11> output EMI SRAM: Add<12> output EMI SRAM: Add<12> output CGND2 CVDD2 Reset State 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 After Boot I/O SPI 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I2C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EMI Z Z Z Z Z Z Z 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 input/output 2mA PP input/output 2mA PP input/output 2mA PP input/output 2mA PP input/output 2mA PP input/output 2mA PP input/output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP supply supply Comments 11/40 TDA7500A I/O DEFINITION AND STATUS (continued) Pin # 52 53 54 55 Function EMI SRAM: Add<13> output EMI SRAM: Add<13> output EMI SRAM: Add<14> output EMI SRAM: Add<14> output EMI SRAM: Add<15> output EMI SRAM: Add<15> output EMI SRAM: Add<16> output EMI SRAM: Add<16> output DSP0:GPIO8 input DSP0: GPIO8 output EMI SRAM: WR output EMI DRAM: WR output EMI SRAM: RD output EMI DRAM: RD output EMI SRAM: ALE output EMI DRAM: CAS output SAI: SDO2 output EMI SRAM: Add<17>output DSP1: GPIO8 input DSP1: GPIO8 output SAI: SDO1 output EMI SRAM: Add<18>output DSP1: GPIO7 input DSP1: GPIO7 output SAI: SDO0 output EMI SRAM: Add<19> output SAI:SDI2 input EMI SRAM: Add<20> output DSP1: GPIO6 input DSP1: GPIO6 output SAI:SDI2 input EMI SRAM: Add<21> output EMI DRAM: RAS output DSP1: GPIO5 input DSP1: GPIO5 output SAI: SDI0 input SPDIF: CD input SAI: SCKT input SAI: SCKT output SAI: LRCKT input SAI: LRCKT output SAI: SCKR input SAI: LRCKR input Reset State 1 1 1 After Boot SPI 1 1 1 I2C 1 1 1 I/O EMI 0/1 0/1 0/1 output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP input output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP output 2mA PP input output 2mA PP output 2mA PP output 2mA PP input output 2mA PP output 2mA PP output 2mA PP input output 2mA PP input output 2mA PP input output 2mA PP output 2mA PP input output 2mA PP input input input output 2mA PP input output 2mA PP input input Comments X 1 1 1 X 1 1 1 X 1 1 1 X 1 1 0 56 57 58 59 X X X X 60 X 1 X 1 X 1 X 1 61 62 X X X X 63 X X X X X X X X X X X X X X X X X X X X X X X X 64 65 66 67 68 12/40 TDA7500A I/O DEFINITION AND STATUS (continued) Pin # 69 Function DSP1 Debug: DBOUT output DSP1: GPIO10 input DSP1: GPIO10 output DSP1 Debug: DBIN input DSP1 : OS10 output DSP1: GPIO11 input DSP1: GPIO11 output DSP1 Debug: DBCK input DSP1 : OS11 output DSP1: GPIO9 input DSP1: GPIO9 output DSP1 Debug: DBRQN input DSP0 Debug: DBOUT output DSP0: GPIO10 input DSP0: GPIO10 output DSP0 Debug: DBIN input DSP0 : OS00 output DSP0: GPIO11 input DSP0: GPIO11 output DSP0 Debug: DBCK input DSP0 : OS01 output DSP0: GPIO9 input DSP0: GPIO9 output DSP0 Debug: DBRQN input GND2 VDD2 ADC<0>input ADC<1>input ADC<2>input ADC<3>input ADC: S2DREF input ADC: ADCVDDREF input X X X X X X X X X X X X X X X X Reset State After Boot SPI 1 X X X X X X X 1 X X X X X X X X X X X X X X 1 X 1 X X X X I2C 1 I/O EMI 1 output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT output 4mA PP input 5VT supply supply analog input analog input analog input analog input Substrate biasing voltage reference connected to GND connect 47F electolytic and 100nF Ceramic parallel to ADCGND connect 100F electolytic and 100nF Ceramic parallel to ADCGND After boot in debug mode After boot in debug mode Comments 70 71 After boot in debug mode 72 73 After boot in debug mode After boot in debug mode After boot in debug mode 74 75 After boot in debug mode 76 77 78 79 80 81 82 83 84 85 ADC: REF<2> input voltage reference 13/40 TDA7500A I/O DEFINITION AND STATUS (continued) Pin # 86 Function ADC: REF<1> input Reset State After Boot SPI I2C I/O EMI voltage reference connect 47F electolytic and 100nF Ceramic parallel to ADCGND connect 47F electolytic and 100nF Ceramic parallel to ADCGND Comments 87 ADC: REF<0> input voltage reference 88 89 90 91 92 93 94 95 96 ADCVDD ADCGND DAC<0> output DAC<1> output DAC<2> output DAC<3> output DAC<4> output DAC<5> output DAC: REF<2> input X X X X X X X X X X X X X X X X X X X X X X X X ADC power supply ADC ground analog output analog output analog output analog output analog output analog output voltage reference connect 47F electolytic and 100nF Ceramic parallel to DACGND connect 47F electolytic and 100nF Ceramic parallel to DACGND (It can be connected to Pin100) connect to DACGND (It can be connected to Pin99) 97 DAC: REF<1> input voltage reference 98 DAC: REF<0> input voltage reference 99 100 DACGND DACVDD DAC ground DAC power supply Output PP: Push-Pull/ OD: Open-Drain 5VT input: TTL Five Volt Tolerant Input - Schmitt-trigger for all inputs. 14/40 TDA7500A PIN CONNECTION (Top view) ADCREF0 ADCREF1 ADCREF2 ADCVDDREF DACGND DACREF0 DACREF1 DACREF2 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 ADCGND ADCVDD ADC1 ADC0 GND2 VDD2 DBRQN0 77 76 DACVDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 S2DREF ADC3 ADC2 DSP0 GPIO0 DSP0 GPIO1 DSP0 GPIO2 DSP0 GPIO3 DSP0 GPIO4 DSP0 GPIO5 DSP0 GPIO6 DSP0 GPIO7 GND1 VDD1 TESTEN TESTSE NRESET SCKM MISOM MOSIM SSM SCKD MISOD MOSID SSD CLKIN AVDD XTI XTO AGND RDSINT RDSARI_SCK RDSQAL_SO RDSDAT_SI RDSCLK_SS INT CGND1 1 2 3 CODEC Test Debug DSP0 4 5 OD OD 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Debug DSP1 IIC/SPI master SAI SPI display SPDIF 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 OD OD DBCK0OS01 DBIN0OS00 DBOUT0 DBRQN1 DBCK1_OS11 DBIN1_OS10 DBOUT1 LRCKR SCKR LRCKT SCKT SDI0 DSP0 GPIO9 DSP0 GPIO11 DSP0 GPIO10 DSP1 GPIO9 DSP1 GPIO11 DSP1 GPIO10 SRCCDC SDI1/SRA<21>/RAS DSP1 GPIO5 SDI2 / SRA<20> DSP1 GPIO6 SDO0 / SRA<19> PLL oscillator SDO1 / SRA<18> DSP1 GPIO7 SDO2 / SRA<17> DSP1 GPIO8 CASALE DRD DWR SRA<16> SRA<15> SRA<14> SRA<13> CVDD2 DSP1 GPIO4 DSP1 GPIO3 DSP1 GPIO2 DSP1 GPIO1 DSP1 GPIO0 EMI RDS OD OD: 5V tolerant Open Drain Output DSP0 GPIO8 SPDIF 26 27 28 29 30 31 32 33 34 35 EMI 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RECOMMENDED DC OPERATING CONDITIONS Symbol VDD VCC Parameter 3.3V Digital Power Supply Voltage 3.3V Analog Power Supply Voltage Test Condition Min. 3.15 3.15 Typ. 3.3 3.3 Max. 3.45 3.45 Unit V V POWER CONSUMPTION Symbol Idd Parameter Total Maximum Current Test Condition power supply @ 3.3V and Tj = 125C Min. Typ. 450 Max. 490 Unit mA Note: 45MHz internal DSP clock, 4ADC and 6DAC enabled. PLL CHARACTERISTICS Symbol Parameter Lock Time (note1) FVCO VCO Frequency (note 2) Test Condition power supply @ 3.3V and Tj = 125C 70 Min. Typ. Max. 3 140 Unit ms MHz Note: 1. Depending on VCO output frequency. 2. Fdsp = Fvco/2 when PLL is running CVDD1 SCRCCD SCRCMD DSRA<7> DSRA<6> DSRA<5> DSRA<4> DSRA<3> DSRA<2> DSRA<1> DSRA<0> SRA<0> SRA<1> SRA<2> SRA<3> SRA<4> SRA<5> SRA<6> SRA<7> SRA<8> SRA<9> SRA<10> SRA<11> SRA<12> CGND2 15/40 TDA7500A OSCILLATOR CHARACTERISTICS Symbol FOSC Parameter Max Oscillator Frequency (XTI) Test Condition power supply @ 3.3V and Tj = 125C Min. Typ. Max. 20 Unit MHz GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol lil lih Ioz IozFT Parameter Low Level Input Current without pullup device High Level Input Current without pullup device Tri-state Output leakage without pull up/down device 5V Tolerant Tri-state Output leakage without pull up/down device I/O latch-up current Electrostatic Protection Test Condition Vi = 0V (note 1) Vi = Vdd (note 1) Vo = 0V or Vdd (note 1) Vo = 0V or Vdd (note 1) Vo = 5.5V V < 0V, V > Vdd Leakage , 1A (note 2) 200 2000 1 Min. Typ. Max. 1 1 1 1 3 Unit A A A A A mA V Ilatchup Vesd Note: 1. The leakage currents are generally very small, <1nA. The value given here, 1mA, ia amaximum that can occur after an Electrostatic Stress on the pin. 2. Human Body Model. LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS Symbol Vil Vih Vhyst Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Schmitt trigger hysteresis Low level output Voltage High level output Voltage Iol = XmA (notes 1, 2) 0.85*Vdd 0.8*Vdd 0.8 0.4 Test Condition Min. Typ. Max. 0.2*Vdd Unit V V V V V Note: 1. Takes into account 200mV voltage drop in both supply lines. 2. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. LOW VOLTAGE TTL INTERFACE DC ELECTRICAL CHARACTERISTICS Symbol Vil Vih Vilhyst Vihhyst Vhyst Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Low level threshold input falling Low level threshold input falling Schmitt trigger hysteresis Low level output Voltage High level output Voltage (note 1) (note 1) (note 1) (note 1) (note 1) Iol = XmA (notes 1, 2 & 3) 2.4 2 0.9 1.3 0.4 1.35 1.9 0.7 0.4 Test Condition Min. Typ. Max. 0.8 Unit V V V V V V V Note: 1. TTL specifications only apply to the supply voltage range Vdd = 3.0V to 3.6V 2. Takes into account 200mV voltage drop in both supply lines. 3. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. 16/40 TDA7500A DSP CORE Symbol Fdsp Parameter Maximum DSP clock frequency Test Condition power supply @ 3.3V and Tj = 125C Min. 48 Typ. Max. Unit MHz FM Stereo Decoder Symbol a_ch THD (S+N)/N Parameter Channel Separation Total Harmonic Distortion Signal plus Noise to Noise ratio Test Condition Min. Typ. >50 0.02 86 Max. Unit dB % dB ADC ELECTRICAL CHARACTERISTCS (Tamb = 25C, VCC = 3.3V, measurement bandwidth 10Hz to 20KHz, A-Weighted Filter.) Symbol Parameter Input Voltage Dynamic Range Sampling rate Attenuation @ 20KHz Dynamic Range SNR (THD + N) Input Impedance Crosstalk Gain mismatch between four input Note1: 0dB reference at 0.75Vrms input Test Condition Min. Typ. 0.75 Max. 0.8 48 Unit Vrms KHz dB dB dB Audio mode @ fs = 44.1KHz -60dB analog input 1KHz; -3dB analog input -3dB analog input (note 1) @ fs = 44.1KHz 1Vrms input @ 1KHz @ 1KHz -0.5 40 84 84 -0.6 88 88 -85 55 -80 75 -85 0.5 dB k dB dB ADC ELECTRICAL CHARACTERISTCS (Tamb = 25C, VCC = 3.3V, measurement bandwidth 10Hz to 53KHz.) Symbol Parameter Input Voltage Dynamic Range Sampling rate Dynamic Range SNR (THD +N) AM-Mode -60dB analog input 1KHz; -3dB analog input -3dB analog input 80 80 -80 Test Condition Min. Typ. 0.75 Max. 0.8 192 Unit Vrms KHz dB dB dB 17/40 TDA7500A ADC ELECTRICAL CHARACTERISTCS (Tamb = 25C, VCC = 3.3V, measurement bandwidth 10Hz to 160KHz.) Symbol Parameter Input Voltage Dynamic Range Sampling rate Dynamic Range SNR FM-Mode -60dB analog input 1KHz; -3dB analog input 60 60 Test Condition Min. Typ. 0.75 Max. 0.8 390 Unit Vrms KHz dB dB DAC PERFORMANCE (Tamb = 25C, VCC = 3.3V, measurement bandwidth 10Hz to 20KHz, A-Weighted Filter 0dB gain, output load 30k) Symbol Parameter Output voltage dynamic range Sampling rate Attenuation @ 20kHz Dynamic Range SNR Digital Silence (THD + N)/S Output Impedance Crosstalk Gain mismatch between six outputs 1Vrms output @ 1KHz @ 1KHz -0.5 @ 20KHz with fs = 44.1KHz -60dB analog input 1KHz -3dB analog output 0000hex digital input @ digital full scale -0.3 90 90 -0.2 93 93 93 -85 25 -90 -83 50 -86 0.5 Test Condition Min. 0.87 Typ. 0.9 Max. 0.93 48 Unit Vrms KHz dB dB dB dB dB dB dB 18/40 TDA7500A SAI INTERFACE Figure 1. SAI Timings SDI0-3 Valid LRCKR Valid t lrh SCKR (RCKP=0) t sckpl tlrs tsdih t sckph tdt tsdis t sckr Timing tsckr tdt tlrs tlrh tsdid tsdih tsckph tsckpl Minimum Clock Cycle Description Value 4TDSP 10 5 5 15 15 0.35 tsckr 0.35 tsckr Unit ns ns ns ns ns ns ns ns SCKR active edge to data out valid LRCK setup time LRCK hold time SDI setup time SDI hold time Minimum SCK high time Minimum SCK low time Note T DSP = dsp master clock cycle time = 1/FDSP Figure 2. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 LRCKR (#68) LEFT RIGHT SCKR (#67) LSB(n-1) SDI0,1,2 (#62, #63, #64) MSB(word n) MSB-1 (n) MSB-2 (n) 19/40 TDA7500A Figure 3. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1. Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. Figure 5. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. 20/40 TDA7500A SPI INTERFACES 10 WORDS MAIN MICRO SPI Symbol Description MASTER tsclk tdtr tmisosetup tmisohold tsclkh tsclkl Clock Cycle Sclk edge to MOSI valid MISO setup time MISO hold time SCK high time SCK high low SLAVE tsclk tdtr tmosisetup tmosihold tsclkh tsclkl Clock Cycle Sclk edge to MOSI valid MOSI setup time MOSI hold time SCK high time SCK high low 12TDSP 40 16 4 0.5tsclk 0.5tsclk ns ns ns ns ns ns 12TDSP 40 16 4 0.5tsclk 0.5tsclk ns ns ns ns ns ns Min Value Unit DISPLAY SPI (different timings) MASTER tsclk Clock Cycle SLAVE tsclk Clock Cycle 6TDSP ns 6TDSP ns Figure 6. SPI Clocking scheme. SSM, SSD (#9, #13) SCLKD, SCLKM (#6, #10) (CPOL=0, CPHA=0) SCLKD, SCLKM (#6, #10) SCLKD, SCLKM (#6, #10) (CPOL=0, CPHA=1) (CPOL=1, CPHA=0) SCLKD, SCLKM (#6, #10) MISOM, MOSIM (#7, #8) MISOD, MOSID (#11, #12) (CPOL=1, CPHA=1) MSB 6 5 4 3 2 1 LSB Internal Strobe for Data Capture 21/40 TDA7500A Debug Port Interface dclk = 40MHz No. 1 2 3 4 5 6 7 8 9 10 DBCK rise time DBCK fall time DBCK Low DBCK High DBCK Cycle Time DBRQN Asserted to DBOUT (ACK) Asserted DBCK High to DBOUT Valid DBCK High to DBOUT Invalid DBIN Valid to DBCK Low (Set-up) DBCK Low to DBIN Invalid (Hold) DBOUT (ACK) Asserted to First DBCK High DBOUT (ACK) Assertion Width 11 12 Last DBCK Low of Read Register to First DBCK High of Next Command Last DBCK Low to DBOUT Invalid (Hold) DBSEL setup to DBCK Characteristics Min. --40 40 200 5 TDSP -3 15 3 2 Tc 4.5 TDSP - 3 7 TDSP + 10 3 TDSP Max. 3 3 ----42 ----5 TDSP + 7 --ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Figure 7. Debug Port Serial Clock Timing. Figure 8. Debug Port Acknowledge Timing. 22/40 TDA7500A Figure 9. Debug Port Data I/O to Status Timing. Figure 10. Debug Port Read Timing. Figure 11. Debug Port DBCK Next Command After Read Register Timing. 23/40 TDA7500A EXTERNAL MEMORY INTERFACE (EMI) DRAM MODE Characteristics Page Mode Cycle Time RAS or RD Assertion to Data Valid CAS Assertion to Data Valid Column Address Valid to Data Valid CAS Assertion to Data Active RAS Assertion Pulse Width (Note 1) (Page Mode Access Only) RAS Assertion Pulse Width (Single Access Only) RAS or CAS Negation to RAS Assertion CAS Assertion Pulse Width Last CAS Assertion to RAS Negation (Page Mode Access Only) Note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6. Timing Mode slow fast slow fast slow fast slow fast 40MHz Unit Min. 10075 ------0 Max. ---159 109 65 40 80 55 -----------ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns slow fast slow fast slow fast slow fast slow fast 264 189 164 114 120 70 65 40 60 35 DRAM Refresh Timing Characteristics RAS Negation to RAS Assertion CAS Negation to CAS Assertion Refresh Cycle Time RAS Assertion Pulse Width RAS Negation to RAS Assertion for Refresh Cycle (Note 1) CAS Assertion to RAS Assertion on Refresh Cycle RAS Assertion to CAS Negation on Refresh Cycle RAS Negation to CAS Assertion on a Refresh Cycle CAS Negation to Data Not Valid Note: 1. Happens when a Refresh Cycle is followed by an Access Cycle. Timing Mode slow fast slow fast slow fast slowf ast slow fast 40MHz Min. 143 93 118 68 325 225 166 116 120 70 18 Max. ----------------Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns slow fast slow fast 160 110 114 64 0 24/40 TDA7500A EXTERNAL MEMORY INTERFACE (EMI) SRAM MODE 40MHz Characteristics Min. Address Valid and CS Assertion Pulse Width Address Valid to RD or WR Assertion RD or WR Assertion Pulse Width RD or WR Negation to RD or WR Assertion RD or WR Negation to Address not Valid Address Valid to Input Data Valid RD Assertion to Input Data Valid RD Negation to Data Not Valid (Data Hold Time) Address Valid to WR Negation Data Setup Time to WR Negation Data Hold Time from WR Negation WR Assertion to Data Valid WR Negation to Data High-Z (Note 1) WR Assertion to Data Active 89 23 45 39 5 --0 73 32 5 --5 Max. -----72 35 ----18 23 -ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Figure 12. External Memory Interface SRAM Read Cycle. SRA_D [7:0] SRA_D [13:8] add. [7:0] data add. [13:8] ALE DRD Figure 13. External Memory Interface SRAM Write Cycle. SRA [7:0] SRA [13:8] add. [13:8] add. [7:0] data ALE DWR 25/40 TDA7500A Figure 14. DRAM Read Cycle. DRA [8:0] Row address 1 Column address 1 Column address 2 Row address 2 RAS CAS DRD nibble 1 DRD [3:0] nibble 2 Figure 15. DRAM Write Cycle. DRA [8:0] Row address 1 Column address 1 Column address 2 Row address 2 RAS CAS DWR nibble 1 DRD[3:0] nibble 2 26/40 TDA7500A SAMPLE RATE CONVERTER Fsin/Fsout = 1 (44.1KHz) Symbol THD+N Parameter Total Harmonic Distortion + Noise Test Condition 20Hz to 20kHz, Full Scale, 16 bit inp. 20Hz to 20kHz, Full Scale, 20 bit inp. 1 kHz 10 kHz 1 kHz 10 kHz DR Dynamic Range Full Scale, 16 bit inp. Full Scale, 16 bit inp. Full Scale, 20 bit inp. Full Scale, 20 bit inp 98 120 0 @ -3 dB from 0 to 20kHz @24.1kHz Fsout = 44.1 kHz 0.7 -0.05 -105 612 1.05 20 +0.05 Min. Typ. Max. -98 -101 -98 -98 -109 -102 Unit dB dB dB dB dB dB dB dB Degree Hz dB dB s 1 kHz -60 dB - 16 bit inp.,A-Weighted 1 kHz -60 dB - 20 bit inp.,A-Weighted IPD fc Rp Rs Tg Fratio Interchannel Phase Deviation Cutoff Frequency Pass Band Ripple Stopband Attenuation Group Delay Fsin / Fsout RDS TIMING Symbol Fcrystal Parameter Crystal Frequency Test Condition First mode Second mode tbclk tdis RDS SPI Bit Clock SPI Disable time between 2 transfers (TDSP is the period of the dsp core) Min. 3TDSP 3TDSP Typ. 8.55 8.664 Max. Unit MHz MHz ns ns The RDS block adhere to the timings defined by the RDS standard EN50067. More information are also available in the dedicated Appllication Note. 27/40 TDA7500A I2C TIMING Figure 16. Definition of Timing for the I2C BUS. Symbol Parameter Test Condition Standard Mode I2C BUS Min. Max. 100 - - Fast Mode I2C BUS Min. 0 1.3 0.6 Max. 400 - - Unit FSCL tBUF tHD:STA SCLl clock frequency Bus free between a STOP and Start Condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated start condition DATA hold time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Data set-up time Capacitive load for each bus line Cb in pF Cb in pF 0 4.7 4.0 kHz s s tLOW tHIGH tSU:STA tHD:DAT tR tF tSU;STO tSU:DAT Cb 4.7 4.0 4.7 0 - - 4 250 - - - - - 1000 300 - -400 1.3 0.6 0.6 0 20+ 0.1Cb 20+ 0.1Cb 0.6 -- - - - 0.9 300 300 - 100 400 s s s s ns ns s ns pF SPDIF TIMING Symbol SPVL SPIR SPHYS Parameter AC input level Input impedance Hysteresis of input @ 1 kHz Test Condition Min. 0.2 - - Typ. 0.5 6 40 Max. 3.3 - - Unit Vpp k mV 28/40 TDA7500A FUNCTIONAL DESCRIPTION The TDA7500A IC broken up into two distinct blocks. One block contains the two DSP Cores and their associated peripherals. The other contains the ADC, DAC and the RDS filter, demodulator and decoder. 24-BIT DSP CORE The two DSP cores are used to process the audio and FM/AM data, coming from the ADC, either any kind of digital data coming via SPDIF or SAI. After the digital signal processing these data are sent to the DAC for analog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the DSP0. When FM/AM mode is selected, DSP1 is fully devoted to AM/FM processing. Nevertheless it can be used for any kind of different application, when a different input source is selected. Some capabilities of the DSPs are listed below: s Single cycle multiply and accumulate with convergent rounding and condition code generation s s s s s s s s s s s s s s s s s s 2 x 56-bit Accumulators Double precision multiply Scaling and saturation arithmetic 48-bit or 2 x 24-bit parallel moves 64 interrupt vector locations Fast or long interrupts possible Programmable interrupt priorities and masking 8 each of Address Registers, Address Offset Registers and Address Modulo Registers Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arithmetic Post-increment or decrement by 1 or by offset, Index by offset, predecrement address Repeat instruction and zero overhead DO loops Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines Bit manipulation instructions possible on all registers and memory locations, also Jump on bit test 4 pin serial debug interface Debug ccess to all internal registers, buses and memory locations 5 word deep program address history FIFO Hardware and software breakpoints for both program and data memory accesses Debug Single stepping, Instruction injection and Disassembly of program memory DSP PERIPHERALS There are a number of peripherals that are tightly coupled to the two DSP Cores. Same of the peripherals are connected to DSP 0 others are connected to DSP1. s 5.5k x 24-Bit Program RAM for DSP0 s s s s s s s 1k x 24-Bit X-Data RAM for DSP0 1k x 24-Bit Y-Data RAM for DSP0 2k x 24-Bit Program RAM for DSP1 1k x 24-Bit X-Data RAM for DSP1 1k x 24-Bit Y-Data RAM for DSP1 Serial Audio Interface (SAI) SPDIF receiver with sampling rate conversion 29/40 TDA7500A s s s s I2C and SPI interface XCHG Interface for DSP to DSP communication External Memory Interface (DRAM/SRAM) for time-delay and traffic information Double Debug Port DATA AND PROGRAM MEMORY Both DSP0 and DSP1 have Data and Program memories attached to them. Each of the memories are described below and it is implied that there are two of each type, one set connected to DSP0 and the other to DSP1. The only exception is the case of the P-RAM where DSP1 has a 2048 x 24-Bit PRAM and DSP0 has a 5.5K x 24Bit PRAM. 1024 x 24-Bit X-RAM (XRAM) This is a 1024 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be written to and read from the Data ALU of the DSP core. The XDBx Bus is also connected to the Internal Bus Switch so that it can be routed to and from all peripheral blocks. 1024 x 24 Bit Y-RAM (YRAM) This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from the Data ALU of the DSP core. The YDBx Bus is also connected to the Internal Bus Switch so that it can be routed to and from other blocks. 2048 x 24-Bit Program RAM (PRAM 5.5K x 24-bit for DSP0) This is a 2048 x 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit PRAM Address, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching, and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PRAM Data (Program Code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding. 512 x 24-Bit Bootstrap ROM (PROM 256 x 24 Bit for DSP1) This is a 512 x 24-Bit factory programmed Boot ROM used for storing the program sequence and for initializing the DSP. Essentially this consists of reading the data via I2C, SPI or EMI interface and store it in PRAM, XRAM, YRAM, and/or external DRAM. 30/40 TDA7500A Figure 17. DSP1 and DSP0 Memory Spaces Boot-Space $FFFF P-Space $FFFF $FFC0 $FFBF X-Space X-Peripherals Y-Space $FFFF $FFFF Boot-Space $FFFF P-Space $FFFF $FFC0 $FFBF X-Space X-Peripherals Y-Space Not Accessible Not Accessible Not Accessible Not Accessible $1600 $15FF Not Accessible Not Accessible Not Accessible Not Accessible P-RAM $0800 $07FF P-RAM $0400 $03FF $0200 $01FF X-RAM Boot-ROM $0000 Y-RAM $0100 $00FF Boot-ROM $0000 X-RAM Y-RAM $0400 $03FF DSP0 DSP1 Serial Audio Interface (SAI) The SAI is used to deliver digital audio to the DSPs from an external source. Once processed by the DSPs, it can be returned through this interface either sent to the DAC for D/A conversion. The features of the SAI are listed below. s 3 Synchronized Stereo Data Transmission Lines s s s 3 Synchronized Stereo Data Reception Lines Master and Slave operating mode: clock lines can be both master and slave. Receive and Transmit Data Registers have two locations to hold left and right data. XCHG Interface (DSP to DSP Exchange Interface) The Exchange Interface peripheral provides bidirectional communication between DSP0 and DSP1. Both 24 bit word data and four bit Flag data can be exchanged. A FIFO is utilized for received data. It minimizes the number of times an Exchange Interrupt Service Routine would have to be called if multi-word blocks of data were to be received. The Transmit FIFO is in effect the Receive FIFO of the other DSP and is written directly by the transmitting DSP. The features of the XCHG are listed below. s 10 Word XCHG Receive FIFO on both DSPs s s Four Flags for each XCHG for DSP to DSP signaling Condition flags can optionally trigger interrupts on both DSPs DRAM/SRAM Interface (EMI) The External DRAM/SRAM Interface is viewed as a memory mapped peripheral. Data transfers are performed by moving data into/from data registers and the control is exercised by polling status flags in the control/status register or by servicing interrupts. An external memory write is executed by writing data into the EMI Data Write Register. An external memory read operation is executed by either writing to the offset register or reading the EMI Data Read Register, depending on the configuration. 31/40 TDA7500A The features of the EMI are listed below. s Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM s s s s s s s Data word length 16 or 24 bits for DRAM Data word length 8 or 16 or 24 bits for SRAM DRAM address lines means 226 = 256MB addressable DRAM Refresh rate for DRAM can be chosen among eight divider factor SRAM relative addressing mode; 2 22 = 4MB addressable SRAM Four SRAM Timing choices Two Read Offset Registers Debug Interface A dedicated Debug Port is available for each DSP Cores. The debug logic is contained in the core design of the DSP. The features of the Debug Port are listed below: s Breakpoint Logic s s s s Trace Logic Single stepping Instruction Injection Program Disassembly Serial Peripheral Interface The DSP core requires a serial interface to receive commands and data over the LAN. During an SPI transfer, data is transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin.The central element in the SPI system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction. I2C Interface The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus. Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality. General Purpose Input/Output The DSP requires a set of external general purpose input/output lines, and a reset line. These signals are used by external devices to signal events to the DSP. The GPIO lines are implemented as DSP 's peripherals. The GPIO lines are grouped in Port A which is connected to DSP 0, and Port B, which is connected to DSP1. RDS The RDS block is an hardware cell able to deliver the RDS frames through a dedicated serial interface. RDS quality signalis also available. This block needs to be initialised at reset by the DSP, after that it works in background and does not need any further DSP support. RDS is made of 57kHz filter, demodulator and decoder. 32/40 TDA7500A Asynchronous Sample Rate Converter The ASRC, embedded in the TDA7500A, offers a fully digital stereo asynchronous sample rate conversion of digital audio sources to the TDA7500A's internal sample frequency. This solves the problem of mixing audio sources with different sample rates and doesn't need the "classical" approach of synchronizing the PLL. As the usual internal sample rate of TDA7500A is around 48.51 kHz, the ASRC works with the common input signals only in upsampling mode. There is no need to explicitly program the input and output sample rates, as the ASRC solves this problem with an automatic Digital Ratio Locked Loop. The ASRC is intended for applications up to 20 bit input word width. Digital Audio Sources can be applied in general Serial Audio Interface format (3 wires) as well as in AES/EBU, IEC and EIAJ CP-340 format (1 wire). An interface to the DSP core offers the possibility of interrupt controlled sample delivery. Furthermore, a programmable Control/Status Register inside the ASRC allows a great variety of adjustments and status informations. Figure 18. shows, how the ASRC interfaces the other blocks. PLL Clock Oscillator The PLL Clock Oscillator can accept an external clock at XTI or it can be configured to run an internal oscillator when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (9 -> 128) in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to generate the internal clock. This allows the internal clock to be within 1 MHz of any desired frequency even when XTI is much greater than 1 MHz. It is recommended that the input clock is not divided down to less than 1 MHz as this reduces the Phase Detector's update rate. The clocks to the DSP can be selected to be either the VCO output divided by 2 to 16, or be driven by the XTI pin directly. The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting a register on DSP0). Figure 18. System Overview Digital Audio Sources e.g.: DAT DAB CD MD Broadcast 48 kHz 48 kHz 44.1 kHz 44.1 kHz 32 kHz lrckr_slv sckr_slv sdi0 AES/EBU IEC 958 EIAJ CP-340 3 1 SAI Receiver Channel 0 S/PDIF Receiver Left [19:0] Right [19:0] Fsin Left [19:0] Right [19:0] Fsin Master Clock Source Fsout * 256 ASRC Asynchr. Sample Rate Converter DSP 33/40 TDA7500A Codec The CODEC is composed of four AD mono converters, three DA stereo converters. The ADC can operate both in audio mode and in FM/AM mode. When in audio mode, it converts the audio bandwidth from 20 to 20KHz. The A to D is a third order Sigma-Delta converter, the converter resolutions is 20 bit with 88 dB of dynamic range and 85dB of total harmonic distortion. When in FM mode, the converted bandwidth is up to 192KHz. The D to A is a third order Sigma-Delta converter with a low noise reconstructing analog filter, the converter resolution is 20 bit with 93 dB of dynamic range and 85dB of total harmonic distortion. All the reference voltages are generated inside the chip. Some capabilities of the CODEC are listed below: s 20-Bit Resolution s s s s s s Digital Anti-Alias Filtering embedded Adjustable System Sampling Rates 93dB D/A Dynamic Range (Not-Weighted)88dB A/D Dynamic Range (Not-Weighted) 85dB D/A (THD+N/S)85dB A/D (THD+N/S) Internal Differential Analog Architecture +3.3V Power Supply SOFTWARE FEATURES A great flexibility is guaranteed by the two programmable DSP cores. A list of the main software functions which can be implemented in the TDA7500A is enclosed hereafter. A block diagram of the audio processing flow is shown in Fig. 19 below. Figure 19. Software Block Diagram of Audio & Sound Processing DLY ANR Stereo input DRC LD B T PEQ SM HP RM DLY DLY DLY DLY Dynamic Loudness Bass Audio noise range reduction compression Treble Parametric Soft mute equaliser LP Routing Delay matrix RF CF LF RR LR SW + ANR DRC LD B T PEQ SM HP AM/FM Baseband Signal Processing s FM weak signal processing s s s Integrated 19 kHz MPX filter and deemphasis flexible noise cancellation flexible multipath detector Generic Audio Signal Processsing s Loudness s s Bass, treble, fader control Volume control 34/40 TDA7500A s s s Distortion Limiting Premium Equalization Soft mute TAPE Signal Processsing s Dolby B Noise Reduction s Automatic Music Search CD Signal Proceessing s Dynamic Range Compression Audiophile Parametric Equalization Crossover Channel Delays Center Channel Imaging Output Audio Noise Reduction s s s s s Other s Voice compression/decompression for TIM storage s Echo and noise cancelling for mobile phone connection Application Scheme The TDA7500A can operate as a standalone device either it can interface the TDA7501 which contains the analog input multiplexer, analog volume control and the line-driver. The FM_MPX and FM_LEVEL signals coming from the tuner and other signals supplied by analog sources are adapted by the TDA7501 and fed to the TDA7500A. A block diagram of the system is shown in Fig. 20 below. The TDA7500A converts all the analog signals into digital domain and performs AM/FM processing and audio/sound processing. Thanks to this, it is possible to process any audio source as well analog as digital in parallel, to record FM mono for traffic information, telephone response, navigation and RDS. Finally the digital signals are D/A converted and sent to the TDA7501 for the final level adjustment and for the analog volume control. 35/40 TDA7500A Figure 20. lock Diagram of Car Amplifier Audio Sub-System. ANALOG INPUT FRONT END TDA7421 2 I C/SPI TDA7501 AUDIO POWER MAIN MICRO A/D D/A DISPLAY MICRO TDA7500A DIGITAL OUT SPDIF EEPROM/ FLASH DIGITAL IN DRAM/ SRAM Fig20TDA7500A Clock Scheme When TDA7500A is used in AD/FM mode the following scheme is choosen in order to avoid harmonics inside the FM band. Parts of the system are directly clocked by the crystal oscillator, whereas other parts are driven by the pll oscillator. Thanks to this it is possible to process any audio source as well analog as digital in parallel to record FM mono for traffic informations, telephone resp. navigation and RDS. Figure 21 shows the clock scheme. Regarding on the country and its FM bandwidth different crystals should be selected. Figure 21. Clock Scheme Fext: 44.1 kHz, 48kHz Fcomp: 1.425 MHz (8.55/6) 1.411 MHz (44.1*2*16) PLL 1.536 MHz (48*2*16) Int./Ext. Stereo DSP 8.55 MHz 8.89 MHz Audio DSP Fdsp: 43.46 MHz (Fvco/4) 39.51 MHz (Fvco/4) 43.01 MHz (Fvco/4) 2nd Hamonics 90.38 86.92 130.38 86.92 90.38 130.38 135.57 Fvco: 173.85 MHz (Fcomp*122) 158.05 MHz (Fcomp*112) 172.03 MHz (Fcomp*112) FM Japan [MHz] 76..90 West Europe East 87.5..108 65..74 OSC Xtal 3rd 135.57 Hamonics A/D FM-rds / noise det. RDS-Demod. Frds: 8.55 MHz (Fxtal) A/D mono level / tel. / navi. Faudio: 48.51 kHz 44.1 kHz 48 kHz Fconverter: 12.42 MHz (Fvco/14) 11.29 MHz (Fvco/14) 12.29 MHz (Fvco/14) A/D FM-mpx/ stereo audio D/A Coverters 36/40 C4 47F C11 47F C13 100F VREF CVDD2 4x 1F R2 10K R3 10K R5 10K R9 10K R7 10K R8 10K R6 10K R10 10K DBCRON0 DBCKOOS01 DBINOOS00 DBOUT0 DBRON1 DBCK1-OS11 DBIN1-OS10 DBOUT1 ADCGND ADCVD00 GND2 VDD2 VDD2 LCRCKR SCKR LRCKT SCKT SDI0 SDI1/SRA21/RAS SDI2/SRA20 SDO0/SRA19 SDO1/SRA18 SDO2/SRA17 CASALE 58 57 56 54 53 52 55 51 29 SRA0 SRA1 SRA2 SRA3 SRA4 SRA5 SRA6 SRA7 DSRA7 DSRA6 DSRA4 DSRA3 DSRA2 DSRA1 DSRA0 DSRA5 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 SRA8 46 SRA9 47 SRA10 48 SRA11 49 SRA12 50 CGND2 DRD DRR SRA15 SRA14 SRA13 SRA16 CVDD2 TO EXT MEMORY TEST I 2C EMI SPI SAI INTERFACE (**) GND2 ADCVD00 ADCGND DEBUG INTERFACE R4 10K NRESET OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 AIN3 AIN2 AIN1 AIN0 CGND2 C14 100nF C15 47F C16 100nF C12 100nF C9 47F C10 100nF ADCGND ADCGND C5 100nF C6 47F APPLICATION DIAGRAM C7 100nF DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 ADC3 ADC2 ADC1 80 76 75 74 73 72 71 70 69 89 88 78 77 68 67 79 S2DREF ADC0 ADCREF2 DACREF1 DACVCC DACREF2 ADCREF0 C8 4.7F 82 81 DACREF0 97 100 96 83 87 95 94 86 ADCREF1 93 92 85 91 90 84 98 Figure 22. Application diagram. DACGND 99 DACGND GND1 1 VDD1 2 TESTEN 3 P TESTSE 4 GND1 C3 10F NRESET 5 SCKW SPI1 MISOM 6 MOSIM 7 GPIO3 SSM 8 SCKO 9 MIOOO 10 66 65 64 63 62 61 60 59 SPI2 MOSIO 11 SSO 12 TDA7500A 13 AVDD CLKIN AVDD 14 AGND AGND 15 XTI 18 ADCVDOREF XTO 16 PIN9 PIN55 GPIO3 GPIO8 0* 0* 0* 1 1 1 0* 1 17 XTAL RDSINT R1 1M RDSARI-SCK 19 C1 22pF C2 22pF RDSQUAL-SO 20 AGND RDS INTERFACES RDSDAT-SI 21 * = Connected to CGND2 = Connected to CVDD2 RDSSCLK-SS 22 INT 23 CGND1 CGND1 24 CVDD1 CVDD1 25 GPIO8 CVDD2 26 27 28 SPDIF1 R11 100 SCRCCD R12 100 SCRCM0 SPDIF2 (**) WHEN NOT USED ALL PINS CONNECTED TO CGND2 TO EXT MEMORY The application diagram shown on the next page must be considered as one of the examples of a (limited) application of the chip. For the real application set-up the application notes are necessary. D00AU1195 TDA7500A 37/40 TDA7500A PACKAGE MARKING 38/40 TDA7500A mm DIM. A A1 A2 B C D D1 D3 e E E1 E3 H L L1 S S1 K ccc 8.80 8.80 0.45 0.05 1.35 0.17 0.09 16.00 14.00 12.00 0.50 16.00 14.00 12.00 9.85 0.60 1.00 0.346 0.346 0 (min.), 3.5 (typ.), 7(max.) 0.080 0.003 0.75 0.018 1.40 0.22 MIN. TYP. MAX. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.003 0.630 0.551 0.472 0.020 0.630 0.551 0.472 0.388 0.024 0.039 0.030 0.055 0.009 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.011 0.008 OUTLINE AND MECHANICAL DATA TQFP100 (14x14x1.40mm) with Slug Down (10x10mm) D D1 D3 SEATING PLANE C A A2 A1 75 76 51 50 ccc C e H S1 E3 E1 E B 0.25mm PIN 1 IDENTIFICATION 100 1 25 26 .010 inch GAGE PLANE C K TQFP100M S L L1 39/40 TDA7500A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 40/40 |
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